A high-level synthesis device is a device that generates synthesis data including a description of an implementation format determined based on input data, when data including a description for realizing a function desired by the user is input. The description contained in the input data is expressed by, such as, a highly abstract model language, a programming language. The description about the implementation format included in the synthesis data is, for example, a description about more specific content than the content about the description included in the input data, and shows a detailed configuration about the circuit. Such a high-level synthesis device is sometimes generally referred to as a high-level synthesis system.
In the present application, it is assumed that a module means one or more groups (one unit, lump) used for realizing a predetermined function, which is constituted by at least one of software and hardware.
Various types of high-level synthesis devices for circuit modules have been proposed. For example, PTL 1 discloses an automatic synthesis device of an inter-module interface corresponding to a high-level synthesis device for a circuit module.
The automatic synthesis device disclosed in PTL 1 analyzes the write sequence and read sequence of the module-to-module interface circuit, obtains the write delay, and analyzes the lifetime of the variables of the variable array of the inter-module interface. Then, the automatic synthesis device derives a degenerated variable set from the set of each variable array, solves the variable sharing problem, and assigns each variable to the memory. The automatic synthesis device synthesizes the circuit based on the assignment of this variable.